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<head><meta charset="utf-8"><title>Inconsistent autovectorization with AVX-512 · general · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/index.html">general</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html">Inconsistent autovectorization with AVX-512</a></h3>

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<a name="248448999"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248448999" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Redzic <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248448999">(Aug 05 2021 at 08:04)</a>:</h4>
<p>Hi, I've been experimenting with writing a specific loop and looking at the generated assembly. I've noticed that <a href="https://godbolt.org/z/Wxenh7qTM">the loop does not always get vectorized</a> (on x86-64-v4) depending on how it is written. I was just wondering if it was possible for some kind of MIR optimization pass or something to transform the loop so that it does get vectorized?</p>



<a name="248449353"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248449353" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Laurențiu <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248449353">(Aug 05 2021 at 08:08)</a>:</h4>
<p>But it does get vectorized if you remove <code>f3</code> or even <code>f2</code></p>



<a name="248450962"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248450962" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> The 8472 <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248450962">(Aug 05 2021 at 08:31)</a>:</h4>
<p>That seems to be quite CPU-arch dependent. On znver3 it doesn't generate any vector instructions at all. So I guess even minor changes could perturb the optimizer?</p>



<a name="248451104"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248451104" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> The 8472 <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248451104">(Aug 05 2021 at 08:33)</a>:</h4>
<p>I guess it doesn't like that the struct size isn't a power of two</p>



<a name="248451249"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248451249" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> The 8472 <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248451249">(Aug 05 2021 at 08:35)</a>:</h4>
<p>It still generates different vector instructions though if you extend/shrink it</p>



<a name="248453118"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248453118" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> The 8472 <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248453118">(Aug 05 2021 at 09:00)</a>:</h4>
<p>I suspect it fails to unify the 3 separate loop variables for the <code>collect</code> implementation. one for the range, one for the write pointer and one for the length.</p>



<a name="248474938"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248474938" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248474938">(Aug 05 2021 at 13:14)</a>:</h4>
<p>minor changes can often perturb the auto-vectorizer. You really can't rely on it happening.</p>



<a name="248513860"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248513860" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Redzic <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248513860">(Aug 05 2021 at 18:06)</a>:</h4>
<p><span class="user-mention silent" data-user-id="330154">The 8472</span> <a href="#narrow/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512/near/248450962">said</a>:</p>
<blockquote>
<p>That seems to be quite CPU-arch dependent. On znver3 it doesn't generate any vector instructions at all. So I guess even minor changes could perturb the optimizer?</p>
</blockquote>
<p>I think the reason it doesn't autovectorize on znver3 is because znver3 doesn't support AVX-512, which seems to be needed to vectorize this specific loop. I wrote the same code in C++, and gcc and clang were also only able to vectorize it if AVX-512 instructions were enabled.</p>



<a name="248525015"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/122651-general/topic/Inconsistent%20autovectorization%20with%20AVX-512/near/248525015" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> The 8472 <a href="https://rust-lang.github.io/zulip_archive/stream/122651-general/topic/Inconsistent.20autovectorization.20with.20AVX-512.html#248525015">(Aug 05 2021 at 19:33)</a>:</h4>
<p>Well, if you change it to 4 fields and target znver3 then it is flipped. The collect loop uses vector instructions while the other two just use a bunch of movs.</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
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